| 1 | Virtex 7 Fpga Implementation Of 256 Bit Key Aes Algorithm With Key Schedule And Sub Bytes Block Optimization | | | |
| 2 | Double Node Upset Immune Rhbd-14t Sram Cell For Space And Satellite Applications | | | |
| 3 | Double Node Upset Immune Rhbd-14t Sram Cell For Space And Satellite Applications | | | |
| 4 | Nwise And Pwise: 10t Radiation Hardened Sram Cells For Space Applications With High Reliability Requirements | | | |
| 5 | Differential Read/Write 7t Sram With Bit-Interleaved Structure For Near-Threshold Operation | | | |
| 6 | Column-Selection-Enabled 10t Sram Utilizing Shared Diff-Vdd Write And Dropped-Vdd Read For Power Reduction | | | |
| 7 | Design Of Low Power High Speed cmos d flip-Flopusing Hybrid Low Power Techniques | | | |
| 8 | 10t Sram Using Half-Vdd Precharge And Row-Wise Dynamically Powered Read Port For Low Switching Power And Ultralow Rbl Leakage | | | |
| 9 | Design Of Acep Multiplier For Wireless Applications With Low Latency | | | |
| 10 | Low Power Multiplier Using Approximate Adder For Error Tolerant Applications | | | |
| 11 | A High-Speed And Low-Leakage Inexact Compressor-Based Approximate Multiplier With Error Encoding Logic | | | |
| 12 | Design And Analysis Of Low-Power And Areaefficient Master-Slave Flip-Flop | | | |
| 13 | Novel Low Power Analog Multiplier/ Divider Cell: A Non-Linear Application Of Vcii | | | |
| 14 | Impact Of Temperature And Process Corners On Read Bit Line Of 8t-Sram Cell For Nor, Nand Operations | | | |
| 15 | Design And Analysis Of Adders Using Pass Transistor Logic For Multipliers | | | |
| 16 | Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging | | | |
| 17 | A Partially Static High Frequency 18t Hybrid Topological Flip-Flop Design For Low Power Application | | | |
| 18 | Energy-Efficient Dual-Node-Upset-Recoverable 12t Sram For Low-Power Aerospace Applications | | | |
| 19 | A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop In 55 Nm Mtcmos | | | |
| 20 | Binary To Gray Code Converter Implementation Using Qca | | | |
| 21 | Design Counter Base Sorting Network Using One Hot Coding | | | |
| 22 | Design Compression Based Sorting Design For High Speed Communication | | | |
| 23 | Design Of Vertibe Decoder For High Speed Communications | | | |
| 24 | Implementation Of Multi Bit Adder For Dsp Applications | | | |
| 25 | Design Of Compressor Based Fir Filter For Dsp Operations | | | |
| 26 | High Speed Efficient Carry Adder Using Reversible Gates | | | |
| 27 | Design Of Posit Adder For Pipeline Techniques | | | |
| 28 | Design Of A Reversible Floating-Point Square Root Using Modi?ed Non Restoring Algorithm | | | |
| 29 | Design And Verification Of Ddr Sdram Memory Controller Using System Verilog For Higher Coverage | | | |
| 30 | Concurrent Error Detectable Carry Select Adder With Easy Testability | | | |
| 31 | The Mesochronous Dual-Clock Fifo Buffer | | | |
| 32 | A High-Performance Multiply-Accumulate Unit By Integrating Additions And Accumulations Into Partial Product Reduction Process | | | |
| 33 | Energy-Ef?cient Low-Latency Signed Multiplier For Fpga-Based Hardware Accelerators | | | |
| 34 | An Ef?cient Parallel Da-Based Fixed-Width Design For Approximate Inner-Product Computation | | | |
| 35 | Design Of Power Ef?cient Posit Multiplier | | | |
| 36 | Design And Analysis Of High Speed Wallace Tree Multiplier Using Parallel Prefix Adders For Vlsi Circuit Designs. | | | |
| 37 | Ef?cient Design For Fixed-Width Adder-Tree | | | |
| 38 | Hardware-Ef?cient Post-Processing Architectures For True Random Number Generators | | | |
| 39 | Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On Fpga | | | |
| 40 | Low-Power Approximate Unsigned Multipliers With Con?gurable Error Recovery | | | |
| 41 | Implementation Of Ripple Carry And Carry Skip Adders With Speed And Area Efficient | | | |
| 42 | Borrow Select Subtractor For Low Power And Area Efficiency | | | |
| 43 | Rapid Balise Telegram Decoder With Modified Lfsr Architecture For Train Protection Systems | | | |
| 44 | A Low-Power Yet High-Speed Configurable Adder For Approximate Computing | | | |
| 45 | High-Speed Area-Ef?cient Vlsi Architecture Of Three-Operand Binary Adder | | | |
| 46 | Design Of 4:2 Compressor For Parallel Distributed Arithmetic Fir Filter | | | |
| 47 | Performance Analysis Of Parallel Prefix Adder For Datapath Vlsi Design | | | |
| 48 | Approximate Reverse Carry Propagate Adder For Energy-Efficient Dsp Applications | | | |
| 49 | Architecture Optimization And Performance Comparison Of Nonce-Misuse-Resistant Authenticated Encryption Algorithms | | | |
| 50 | Tosam:Anenergy-Efficienttruncation-Androunding-Basedscalableapproximate Multiplier | | | |
| 51 | Design And Analysis Of Approximate Redundant Binary Multipliers. | | | |
| 52 | Rounding Technique Analysis Of Power-Area & Energy Efficient Approximate Multiplier Design | | | |
| 53 | A Combined Arithmetic-High-Level Synthesis Solution To Deploy Partial Carry-Save Radix-8 Booth Multipliers In Datapath. | | | |
| 54 | Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors. | | | |
| 55 | Efficient Modular Adder Designs Based On Thermometer & One-Hot Encoding | | | |
| 56 | Error Detection And Correction In Sram Emulated Tcams | | | |
| 57 | Efficient Design For Fixed Width Adder Tree | | | |
| 58 | Area ?Time Efficient Streaming Architecture For Architecture For Fast And Brief Detector | | | |
| 59 | Hard Ware Efficient Post Processing Architecture For True Random Number Generators | | | |
| 60 | A Two Speed Radix -4 Serial ?Parallel Multiplier | | | |
| 61 | Low Power Approximate Unsigned Multipliers With Configurable Error Recovery | | | |
| 62 | Energy Quality Scalable Adders Based On Non Zeroing Bit Truncation | | | |
| 63 | Double Mac On A Dsp Boosting The Performance Of Convolutional Neural Networks On Fpgas | | | |
| 64 | A Low-Power Parallel Architecture For Linear Feedback Shift Registers | | | |
| 65 | Ultra-Low-Voltage Gdi-Based Hybrid Full Adder Design For Area And Energy-Efficient Computing Systems | | | |
| 66 | Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- Swing Gdi Technique | | | |
| 67 | Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic In 130-Nm Cmos For Large-Scale Array Applications | | | |
| 68 | Low-Power Near-Threshold 10t Sram Bit Cells With Enhanced Data-Independent Read Port Leakage For Array Augmentation In 32-Nm Cmos | | | |
| 69 | Column Selection Enabled 10 T Sram Utilizing Shared Diff Vdd Write And Dropped Vdd Read For Fft On Real Data. | | | |
| 70 | Cell-State-Distribution ?Assisted Threshold Voltage Detector For Nand Flash Memory | | | |
| 71 | Efficient Vlsi Implementation Of A Sequential Finite Field Multiplier Using Reordered Normal Basis In Domino Logic | | | |
| 72 | An Approach To Lut Based Multiplier For Short Word Length Dsp Systems | | | |
| 73 | Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based On Quaternary Signed Digit Number System | | | |
| 74 | Fpga Implementation Of An Improved Watchdog Timer For Safety-Critical Applications | | | |
| 75 | Unbiased Rounding For Hub Floating-Point Addition | | | |
| 76 | A Low-Power Yet High-Speed Configurable Adder For Approximate Computing | | | |
| 77 | A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design | | | |
| 78 | The Design And Implementation Of Multi ? Precision Floating Point Arithmetic Unit Based On Fpga | | | |
| 79 | Extending 3-Bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction | | | |
| 80 | Efficient Modular Adders Based On Reversible Circuits | | | |
| 81 | Maes: Modified Advanced Encryption Standard For Resource Constraint Environments | | | |
| 82 | Chip Design For Turbo Encoder Module For In-Vehicle System | | | |
| 83 | Low-Power And Fast Full Adder By Exploring New Xor And Xnor Gates | | | |
| 84 | Low Power 4_4 Bit Multiplier Design Using Dadda Algorithm And Optimized Full Adder | | | |
| 85 | Low Leakage Fully Half-Select-Free Robust Sram Cells With Bti Reliability Analysis | | | |
| 86 | Improved 64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction | | | |
| 87 | Clock-Gating Of Streaming Applications For Energy Efficient Implementations On Fpgas | | | |
| 88 | An Improved Dcm-Based Tunable True Random Number Generator For Xilinx Fpga | | | |
| 89 | Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing | | | |
| 90 | Dlau: A Scalable Deep Learning Accelerator Unit On Fpga | | | |
| 91 | Overloaded Cdma Crossbar For Network-On-Chip | | | |
| 92 | Design Of Power And Area Efficient Approximate Multipliers | | | |
| 93 | Scalable Approach For Power Droop Reduction During Scan-Based Logic Bist | | | |
| 94 | Design Of Low-Power High-Performance 2-4 And 4-16 Mixed-Logic Line Decoders. | | | |
| 95 | Performance Analysis Of A Low-Power High-Speed Hybrid 1-Bit Full Adder Circuit | | | |
| 96 | 12t Memory Cell For Aerospace Applications In Nano Scale Cmos Technology | | | |
| 97 | Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding | | | |
| 98 | Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic | | | |
| 99 | Low-Cost High-Performance Vlsi Architecture For Montgomery Modular Multiplication | | | |
| 100 | A High-Speed Fpga Implementation Of An Rsd-Based Ecc Processor | | | |
| 101 | Hybrid Lut/Multiplexer Fpga Logic Architectures | | | |
| 102 | In-Field Test For Permanent Faults In Fifo Buffers Of Noc Routers | | | |
